Memory modules are widely used in a variety of electronic systems, especially Personal Computers (PC's). Memory modules are built to meet specifications set by industry standards, thus ensuring a wide potential market. High-volume production and competition have driven module costs down dramatically, benefiting buyers of a wide variety of electronic systems.
Memory modules are made in many different sizes and capacities, such as older 30-pin and 72-pin single-inline memory modules (SIMMs) and newer 168-pin, 184-pin, and 240-pin dual inline memory modules (DIMMs). The “pins” were originally pins extending from the module's edge, but now most modules are leadless, having metal contact pads or leads. The modules are small in size, being about 3-5 inches long and about an inch to an inch and a half in height.
The modules contain a small printed-circuit board substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnect layers. Surface mounted components such as DRAM chips and capacitors are soldered onto one or both surfaces of the substrate.
FIG. 1 shows an illustration of a fully-buffered memory module. Memory module 10 contains a substrate such as a multi-layer printed-circuit board (PCB) with surface-mounted DRAM chips 22 mounted to the front surface or side of the substrate, as shown in FIG. 1, while more DRAM chips 22 are mounted to the back side or surface of the substrate (not shown). Memory module 10 could be a fully-buffered dual-inline memory module (FB-DIMM) that is fully buffered by an Advanced Memory Buffer (AMB) chip (not shown) on memory module 10. The AMB chip uses differential signaling and packets to transfer data at high rates.
Memory modules without an AMB chip are still being made. Such unbuffered memory modules carry address, data, and control signals across metal contact pads 12 from the motherboard directly to DRAM chips 22. Some memory modules use simple buffers that buffer or latch some of these signals but do not use the more complex serial-packet interface of a FB-DIMM.
Metal contact pads 12 are positioned along the bottom edge of the module on both front and back surfaces. Metal contact pads 12 mate with pads on a module socket to electrically connect the module to a PC's motherboard. Holes 16 are present on some kinds of modules to ensure that the module is correctly positioned in the socket. Notches 14 also ensure correct insertion of the module. Capacitors or other discrete components are surface-mounted on the substrate to filter noise from the DRAM chips 22.
Some memory modules include a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module substrate. SPD-EEPROM 130 stores configuration information for the memory module, such as speed, depth, and arrangement of the memory on the memory module.
DRAM chips may have a very large capacity, such as 512 Mbits, or half a giga-bit. The large number of memory cells, small size of individual memory cells, and overall large area of the DRAM die cause manufacturing defects to be somewhat common. DRAM chips are tested on a wafer before being separated and packaged, but this wafer-sort test may not catch all defects. A probe card is used to make contact with individual die on the wafer, causing a very noisy test environment. Thus test speeds are limited at wafer sort, preventing more exhaustive testing that could catch more defects.
Thus some packaged DRAM chips are going to contain defects. Further testing of packaged DRAM chips may be performed cost-effectively at higher speeds, allowing defective DRAM chips to be identified and discarded. However, discarding packaged DRAM chips is somewhat wasteful, since often only a single defect is present. For example, a defect may cause only 1 of the half-billion memory cells to fail. Nearly half a billion memory cells operate properly on a DRAM chip having a single defect, yet this chip is typically discarded.
Some DRAM chips are repairable. A fuse on the die may be blown using a laser during wafer sort, or some other method may be used. This repair may be attempted and performed to determine which DRAM chips are good and which are bad, or repair may be a separate step. Repair often causes the full size of memory to be available when repair is successful. For example, repairing a bad memory cell on a 512 Mbit DRAM allows a full 512 Mbits to be usable, since the bad memory cell is replaced by a redundant memory cell during repair.
Rather than repairing chips, some chip manufacturers may downgrade DRAM chips to lower capacities. For example, a 1 giga-bit DRAM die with a defect may be partially-good, packaged, and sold as a half giga-bit DRAM.
Manufacturers of memory modules may purchase packaged DRAMs that have a variety of levels of testing already performed. Cost may be reduced by purchasing packaged DRAMs that have not yet been exhaustively tested. The memory module manufacturer may arrange to more fully test these incoming DRAM chips to weed out DRAM chips with single defects.
FIGS. 2A-B show a defect on a partially-good DRAM chip. In FIG. 2A, DRAM chip has an upper address bit A13 that divides the memory into two halves H1, H2. The halves H1, H2 may be logical halves rather than separate physical arrays on the DRAM die. When address A13=1, half H2 is selected, while when A13=0, half H1 is selected. Defect 56 occurs when A13 is 1, so defect 56 is in H2 half 552. Since all bits with A13=0 are good, H1 half 554 is a good half and could be usable on a memory module.
Sometimes two or more defects may occur. When defects occur in both halves 552, 554, there is no half that is usable. However, the DRAM chip can be further divided into quadrants. In FIG. 2B, upper address bits A13, A12 have four possible values, creating four quadrants 562, 564, 566, 568, also labeled Q4, Q3, Q2, Q1. For example, for memory cells addressable by A13=1 and A12=0, Q3 quadrant 564 is selected.
When defects occur in only two of the four quadrants, the remaining two quadrants may be combined to form a half-size DRAM. For example, when defects occur in Q3, Q2 quadrants 564, 566, the remaining Q4, Q1 quadrants 562, 568 may be used as a half-size memory.
FIG. 3 illustrates a prior-art burn-in test flow for making memory modules. DRAM dice are made in a factory or wafer fab and are tested and packaged as DRAM chips 22. Some wafer-sort testing may be performed to determine which die to package and which die to discard.
Packaged DRAM chips 22 are initially tested by being placed into test socket 108, which connects to ATE test head 102 of an automated-test-equipment (ATE). ATE testers are very expensive, typically being million-dollar machines. DRAM chips 22 that pass testing on ATE test head 102 are inserted into test sockets on memory-chip burn-in board 106. Once populated with many DRAM chips 22, memory-chip burn-in board 106 is inserted into burn-in oven 104 for several hours, days, or weeks of applied stress.
A stress voltage may be applied to the power-supply or other pins of DRAM chips 22 by memory-chip burn-in board 106 while inside burn-in oven 104. This allows DRAM chips 22 to be stressed by both high heat and high voltage, such as 125 degrees C. and 5.5 volts. Applied voltages to signal pins may be toggled high and low for added stress.
After a period of time in burn-in oven 104, memory-chip burn-in board 106 is removed from burn-in oven 104 and DRAM chips 22 are removed from test sockets on memory-chip burn-in board 106. DRAM chips 22 are then tested again on ATE test head 102, and failing chips are discarded. If the period of time in burn-in oven 104 is sufficiently long, failures known as infant mortalities can be screened out, increasing reliability of the remaining DRAM chips 22.
DRAM chips 22 that pass the post-burn-in test on ATE test head 102 are soldered to substrate boards during assembly of memory module 10. Memory modules may then be tested, either on ATE test head 102 or on another tester, and shipped to customers.
A single memory module may contain several DRAM chips, such as 8 or more DRAM chips per module. Each of these 8 or more DRAM chips 22 must be inserted into test sockets on memory-chip burn-in board 106 before insertion into burn-in oven 104, and each of the 8 or more DRAM chips 22 must be removed from these test sockets on memory-chip burn-in board 106 after removal from burn-in oven 104. Inserting and removing DRAM chips into test sockets on memory-chip burn-in board 106 may be performed manually, which is tedious and time consuming.
A disadvantage of this burn-in process is that each memory module with 8 DRAM chips requires 8 insertions and 8 removals, or a total of 16 insertion/removal steps per module with 8 DRAM chips. A human operator likely can only insert or remove one DRAM chip at a time.
What is desired is memory module that can be constructed with partially-good DRAM chips. A manufacturing and testing method to make memory modules from partially-good memory chips is desirable. A process to test partially-good DRAM chips, store defect maps, and use the partially-good chips on memory modules is desirable.